reducing hardware complexity of wallace multiplier using high order compressors based on cntfet

multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and reduce the area of multipliers. compressors are adders which can be used to perform the partial product addition in wallace tree. on the other hand, using new emerging technologies such as carbon nanotube field effect transistors (cntfet) leads to provide implementations faster and smaller circuits. this paper presents a new method to reduce the simplification of wallace tree design using high order compressors based on carbon nanotube technology. these compressors use a high-speed full adder cell based on cntfets for low-voltage and high-frequency applications. the proposed method reduces the number of gates and transistors, critical path length and complexity of the wallace tree hardware.